Jingxin Microelectronics has successfully taped out and brought up two self‑developed RapidIO chips – the SR1820 switch and ST0420 bridge – on August 18, with all core function tests completed within one hour.
The SR1820 is a low‑latency high‑speed switch with 24 ports / 48 lanes, delivering 600Gbps aggregate switching capacity at 1.25–12.5Gbaud per lane – double the performance of its predecessor. Minimum packet forwarding latency hits 100ns. It features plug‑and‑play and congestion detection, and interoperates seamlessly with MCUs, DSPs, FPGAs, ASICs, and bridge devices.
The ST0420 is a hardware protocol bridge between RapidIO and PCIe. Its built‑in address mapping engine enables direct data conversion without host CPU intervention, supporting large‑scale high‑speed transfers and RDMA. The RapidIO side offers 4 lanes at 12.5Gbaud (50Gbps line‑rate conversion) with sub‑200ns latency.
When paired, the two chips enable GPU Direct RDMA for AI parallel computing, delivering >40Gbps bandwidth and hundreds‑of‑nanoseconds latency – building a high‑performance I/O interconnect fabric for domestic AI clusters and embedded systems.
ICgoodFind Takeaway:
These two RapidIO chips fill a critical gap in domestic high‑speed interconnect silicon – a strong boost for AI parallel computing and embedded ecosystems in China.
